Since the 1990's, integrated circuit (IC) design has evolved from a chip-set philosophy to an embedded core based SoC concept. An SoC IC includes various reusable functional blocks, such as microprocessors, interfaces, memory arrays, and DSPs (digital signal processors). Such pre-designed functional blocks are commonly called “IP cores”, “cores”, or “blocks”, and will collectively be referred to hereafter as “functional blocks” or simply, “blocks”. The resulting SoCs have become quite complex. Moreover, the techniques used in the design of these SoCs have not scaled with the complexities of chip designs. That is, SoCs are currently designed by combining functional blocks from different vendors into a single design. Prior to their incorporation on the SoC, these functional blocks typically will have been subjected to various production testing procedures, to include scan chain tests. Scan chain testing is well-known in the prior art and permits determining the internal states of various memories and registers contained on the functional block. In addition to prior testing of the component functional blocks, the interfaces between these blocks are functionally verified by various well-know techniques. Frequently, problems in the resulting SoC are encountered in spite of these two levels of testing. Moreover, if there are problems in a design after the device has been fabricated, it may be extremely difficult to determine the cause of the problems. This difficulty can be attributed to the number of functional blocks that are potential sources of the problem and the lack of visibility of the internal operation of the SoC device. Additionally, the operation of the device can differ significantly from the simple functional vectors that are typically used to verify the interfaces of the functional blocks.
Various prior art methods exist whereby designers take preventive steps for avoiding problems with their SoC designs. Preventive steps include writing many vectors to check the functionality of a device and running code coverage tools to evaluate the test results. In spite of such efforts, functional problems do occur in fabricated devices. The likelihood of functional problems occurring increases with the complexity of the SoC. For such complex systems, it is virtually impossible to write vectors to test all the different combinations of functional operation of functional blocks. Moreover, there may be functional features that the designer did not think about testing. Further, the functional problem may occur after extended periods of operation and accordingly cannot be easily detected by running simple test vectors.
When functional problems do occur with fabricated SoCs, designers attempt to determine the cause by observing the state of internal registers, internal memories, or by monitoring the outputs of the pins to the device (e.g., by various prior art means such as test probing of the device pins as well as more sophisticated methods employing computer driven debugging interfaces). Often, there is insufficient visibility to the internal state of the SoC device. In such cases, the designer must speculate as to what the cause of the functional failure is. As a result, it may take several revisions to the circuit design before the problem is corrected.
Lacking in the prior art is a more accurate means of determining the internal state of an SoC device to thereby better determine the nature of a failure and thereby more efficiently effect a remedy.